Modern-day semiconductor devices, commonly called integrated circuits, or “dies,” are fabricated on wafers, and the wafers are then sawn into grids, separating the individual dies prior to assembly in a package. Integrated circuits are fabricated in a variety of sizes, but typically range from only a few millimeters to a couple of centimeters or more in width. Each die may have numerous electrical signals for input or output. Processors, for example, may have several hundred signals.
Provisions must be made to electrically connect a die to the printed circuit board with which it is used and also to protect the die from damage or other external conditions that could hinder its operation. Package engineering, or packaging, is the field within semiconductor engineering that addresses these needs. Integrated circuits are generally mounted on printed circuit boards in “packages,” i.e., structures that provide an electrical interface with a printed circuit board (or simply “board”) and also protect a bare die and its electrical interconnects from damage, including damage due to moisture, vibration, and impact. A packaged die is generally attached to a metal leadframe or a substrate, electrically connected to the leadframe or substrate, and encapsulated with a ceramic enclosure or plastic “mold compound” for protection.
Occasionally, conventional packaging solutions may not afford adequate space savings on a printed circuit board. Especially in the case of memory devices, the functionality of multiple dies may be required while space for only one packaged die is available on a board. In such cases, using a “multi-chip module” (MCM), or single package containing multiple dies, is often considered. In some MCM's, dies are arranged side-by-side on a single substrate. However, depending on the application, this approach may not provide significant space savings over simply packaging multiple dies separately, a more common assembly process. Accordingly, it may be desired to stack multiple dies within a single package.
There are several benefits to stacked die packages. More functionality within a given area of board space may be achieved, since more silicon functions per area of board space (and per unit volume of application space) are possible. Eliminating individual packages for each die can contribute to significant size and weight reductions of printed circuit boards and electronic devices in which they are installed. Including two or more dies in one package decreases the number of components mounted on an application board, potentially reducing overall system cost. In addition, providing a single package for package assembly, electrical testing and handling may reduce manufacturing costs.
In some cases, it is desirable to package multiple identical dies in a single package, such as in the case of certain memory devices. As an example, four identical 8-megabyte (Mb) dies could be interconnected to act as a single 32-Mb device. In addition, a 16- or 24-Mb device could be assembled on the same package substrate or board by interconnecting two or three of these dies, respectively, without the need for designing and fabricating an additional die design.
Stacking and electrically interconnecting several identical dies has proved problematic, since each identical die will have the exact same internal structures, circuitry, and pattern of bond pads. Consequently, it is difficult to route multiple identical dies to a substrate or motherboard through those dies below it, since an active feature on one die would require an area free of active circuitry on the die beneath it in order to pass through and connect with the substrate or board. A need exists to provide a low-profile solution for interconnecting multiple identical stacked dies.